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Micrel, Inc.
KSZ9692PB, KSZ9692PB-S
frame’s destination.
If the network controller scans a frame and does not find the specific sequence shown above, it discards the frame and
takes no further action. If the KSZ9692PB, KSZ9692PB-S controller detects the data sequence, however, it then alerts the
device’s power management circuitry to wake up the system.
IPv6 Support
The KSZ9692PB, KSZ9692PB-S provides the following IPv6 support in the hardware:
? Generates the checksum for IPv6 TCP/UDP packets based on register configuration (LAN MAC DMA Transmit
Control Register and WAN MAC DMA Transmit Control Register) or Transmit Descriptor 1 (TDES1). The register
setting is static configuration and the TDES1 setting is packet based configuration.
? Filters IPv6 packets with TCP/UDP errors (LAN MAC DMA Receive Control Register and WAN MAC DMA Receive
Control Register).
? Supports up to 8 Source IP or Destination IP based filtering (LAN/WAN Access Control List)
Refer to the Register Description Document for more details.
DMA Controller
Integrated DMA controller connects data port of IP Security Engine, two Gb Ethernet MACs, two USB 2.0 ports, PCI 2.3
bus interface, and SDIO interface via dedicated channels to DDR memory controller for moving large amounts of data
without significant ARM processor intervention. A typical DMA channel usage is to move data from these interfaces into
DDR memory. The data in the memory is processed by the ARM processor and driven back by the DMA channel to the
external interface. Additionally, the ARM processor itself has a dedicated DMA channel to access the DDR memory
controller. Flash/ROM/SRAM, NAND controller, and peripherals do not have dedicated DMA channel and therefore
depend on the ARM processor for transfer of data to DDR memory. DMA channel interfaces are shown in the functional
block diagram on page 7.
The arbitration of all requests from DMA channels are handled by the DDR memory controller and pipelined for best
performance. The memory controller supports programmable bandwidth allocation for each DMA channel, thus enabling
the designer to optimize I/O resource utilization of memory.
UART Interface
The KSZ9692PB, KSZ9692PB-S support four independent high-speed UARTs; UART1, UART2, UART3 and UART4. The
UART ports enhance the system availability for legacy serial communication application and console port display.
UART1, UART2, UART3 and UART4 support maximum baud rate of 5 Mbps including standard rates. The higher rates
allow for Bluetooth and GSM applications.
UART1 supports CTSN, DSRN, DCDN modem control pins in addition to RXD and TXD data pins. For UART2, UART3,
UART4 only CTSN and RTSN control pins in addition to RXD and TXD data pins are supported.
Timers and Watchdog
Two programmable 32-bit timers with one capable of watchdog timer function. These timers can operate in a very flexible
way. The host can control the timeout period as well as the pulse duration. Both timers can be enabled with interrupt
capability. When the watchdog timer is programmed and the timer setting expires, the KSZ9692PB, KSZ9692PB-S resets
itself and also asserts WRSTO to reset other devices in the system.
GPIO
Twenty general purpose I/O (GPIO) are individually programmable as input or output. Some GPIO ports are
programmable for alternate function as listed below:
?
?
?
?
?
Four GPIO programmable as inputs for external interrupts
Two GPIO programmable as 32-bit timers output
Six GPIO programmable as CTSN and RTSN control pins for UART2, UART3, UART4
One GPIO programmable as SDIO Line Status LED driver
One GPIO programmable as ARM CPU interrupt line activity.
See Signal Description list for detailed GPIO map.
May 2011
39
M9999-051111-4.0
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